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Murnal, Vyas R.
- An Improved Nanoscale Quasi-Ballistic Double Gate (DG) Mosfet Model with Drain Bias Dependency on Critical Channel Length Near The Low Field Source Region by Semi-Empirical Approach
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Authors
Vyas R. Murnal
1,
C. Vijaya
1
Affiliations
1 Department of Electronics and Communication Engineering, Shri Dharmasthala Manjunatheshwara College of Engineering and Technology, IN
1 Department of Electronics and Communication Engineering, Shri Dharmasthala Manjunatheshwara College of Engineering and Technology, IN
Source
ICTACT Journal on Microelectronics, Vol 6, No 4 (2021), Pagination: 1020-1026Abstract
This work presents a physically accurate drain current model valid for Double Gate MOSFETs in the nanoscale regime. The model incorporates both diffusive and ballistic carrier transport on the basis of scattering theory. The significance of carrier scattering at the critical channel length near the low field source region is illustrated. The proposed model presents a semi-empirical approach to determine the critical channel length as a function of drain bias applicable for symmetric Double Gate MOSFETs. Fermi-Dirac statistics and Carrier degeneracy are considered in this work for optimal physical accuracy. The proposed quasi-ballistic model captures the signature effect of short channel devices and also exhibits good continuity in terms of drain current, terminal charges and capacitances. A relative analysis of the proposed quasi-ballistic model is done with other recent works.Keywords
Diffusion, Quasi-Ballistic Transport, Scattering, Critical Channel Length, DG MOSFETs.
References
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- Vyas Murnal and C. Vijaya, “A Quasi-Ballistic Drain Current, Charge and Capacitance Model with Positional Carrier Scattering Dependency Valid for Symmetric DG MOSFETs in Nanoscale Regime”, Nanoconvergence, Vol. 6, No. 19, pp. 1-17, 2019.
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- Mark R. Pinto and Kent Smith Padre, Available at https://nanohub.org/resources/padre, Accessed at 2020.
- S. Khandelwal, H. Agarwal, P. Kushwaha, J.P. Duarte, A. Medury, Y.S. Chauhan, S. Salahuddin and C. Hu, “Unified Compact Model Covering Drift-Diffusion to Ballistic Carrier Transport”, IEEE Electron Device Letters, Vol. 37, No. 2, pp. 134-137, 2016.
- Comparative Analysis of Diverse Carrier Transports in Multigate MOSFETS Under Different Channel Length Regimes
Abstract Views :210 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Shri Dharmasthala Manjunatheshwara College of Engineering and Technology, IN
1 Department of Electronics and Communication Engineering, Shri Dharmasthala Manjunatheshwara College of Engineering and Technology, IN
Source
ICTACT Journal on Microelectronics, Vol 7, No 3 (2021), Pagination: 1171-1177Abstract
Multi-gate MOSFETs have successfully enabled the extension of CMOS technology scaling in the nanoscale regime. Suppression of short channel effects (SCEs) and carrier transport enhancement are the two prime factors that matter the most for the improvements in digital CMOS technology. Multi-gate transport leads to suppression of SCEs and mobility improvement leads to carrier transport enhancement. Continuous scaling of device channel length in the nanoscale regime invites for the inclusion of scattering theory physics. The proposed work discusses the diverse carrier transport mechanisms occurring in Multi-gate MOSFETs in different channel length regimes. Further, a comparative analysis of carrier transport in long, short and ultra-short channel Multi-gate devices is done. The work also discusses the validity of the transport models and their scaling restrictions in different regimes. The simulation results demonstrate physical accuracy and continuity of the proposed models in the respective channel length regimes.Keywords
Diffusion, Quasi-Ballistic Transport, Scaling, Carrier Scattering, Multi-Gate MOSFETs.References
- J.P. Colinge, “Multiple-Gate SOI MOSFETs”, Solid State Electronics, Vol. 48, No. 6, pp. 897-905, 2004.
- Y. Taur, J. Song and B.Yu, “Compact Modeling of Multiple-Gate MOSFETs”, Proceedings of International Conference on Solid-State and Integrated-Circuit Technology, pp. 258-261, 2008.
- D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur and H.P. Wong, “Device Scaling Limits of Si MOSFETs and their Application Dependencies”, Proceedings of the IEEE, Vol.89, No.3, pp.259-288, 2001.
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- M. Lundstrom and Z. Ren, “Essential Physics of Carrier Transport in Nanoscale MOSFETs”, IEEE Transactions on Electron Devices, Vol. 49, No. 1, pp.133-141, 2002.
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- V. Murnal and C. Vijaya, “An Improved Nanoscale Quasi-Ballistic Double Gate (DG) MOSFET Model with Drain Bias Dependency on Critical Channel Length near the Low Field Source Region by Semi-Empirical Approach”, Indian Journal of Microelectronics, Vol. 6, No. 4, pp. 1020-1026, 2021.
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